JPH0250738U - - Google Patents
Info
- Publication number
- JPH0250738U JPH0250738U JP12715788U JP12715788U JPH0250738U JP H0250738 U JPH0250738 U JP H0250738U JP 12715788 U JP12715788 U JP 12715788U JP 12715788 U JP12715788 U JP 12715788U JP H0250738 U JPH0250738 U JP H0250738U
- Authority
- JP
- Japan
- Prior art keywords
- driver gate
- inhibit input
- data bus
- drives
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
- Power Sources (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12715788U JPH0250738U (en]) | 1988-09-30 | 1988-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12715788U JPH0250738U (en]) | 1988-09-30 | 1988-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0250738U true JPH0250738U (en]) | 1990-04-10 |
Family
ID=31379330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12715788U Pending JPH0250738U (en]) | 1988-09-30 | 1988-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0250738U (en]) |
-
1988
- 1988-09-30 JP JP12715788U patent/JPH0250738U/ja active Pending
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